发明授权
US07616039B2 Memory reset apparatus 失效
存储器复位装置

Memory reset apparatus
摘要:
A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.
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