Invention Grant
- Patent Title: Semiconductor device with multiple silicide regions
- Patent Title (中): 具有多个硅化物区域的半导体器件
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Application No.: US11688592Application Date: 2007-03-20
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Publication No.: US07629655B2Publication Date: 2009-12-08
- Inventor: Chen-Hua Yu , Cheng-Tung Lin , Chen-Nan Yeh
- Applicant: Chen-Hua Yu , Cheng-Tung Lin , Chen-Nan Yeh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.
Public/Granted literature
- US20080230844A1 Semiconductor Device with Multiple Silicide Regions Public/Granted day:2008-09-25
Information query
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