发明授权
- 专利标题： Multiplex bus system with duty cycle correction
- 专利标题（中）： 具有占空比校正功能的多路复用总线系统
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申请号： US10360436申请日： 2003-02-07
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公开(公告)号： US07636410B2公开(公告)日： 2009-12-22
- 发明人: Geert Maria Marcel Vandensande
- 申请人： Geert Maria Marcel Vandensande
- 申请人地址： US AZ Phoenix
- 专利权人： Semiconductor Components Industries, LLC
- 当前专利权人： Semiconductor Components Industries, LLC
- 当前专利权人地址： US AZ Phoenix
- 代理机构： Barnes & Thornburg LLP
- 优先权： EP02290332 20020211
- 主分类号： H04L7/00
- IPC分类号： H04L7/00
摘要：
The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.
公开/授权文献
- US20030154418A1 Multiplex bus system with duty cycle correction 公开/授权日：2003-08-14
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