发明授权
- 专利标题: Non-volatile semiconductor memory
- 专利标题(中): 非易失性半导体存储器
-
申请号: US12257828申请日: 2008-10-24
-
公开(公告)号: US07639544B2公开(公告)日: 2009-12-29
- 发明人: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- 申请人: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- 申请人地址: JP Kawasaki-shi, Kanagawa-ken
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Kawasaki-shi, Kanagawa-ken
- 代理机构: Banner & Witcoff, Ltd.
- 优先权: JP2000-063798 20000308; JP2000-323199 20001023
- 主分类号: G11C11/34
- IPC分类号: G11C11/34 ; G11C16/06
摘要:
A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
公开/授权文献
- US20090052254A1 Non-Volatile Semiconductor Memory 公开/授权日:2009-02-26
信息查询