A transmitter and/or receiver includes a single crystal clock oscillator circuit and a sample rate converter (SRC) that selectively generates samples at an alternative frequency for subsequent transmission or decoding. A 40 MHz crystal provides the clock signal for the digital-to-analog and analog-to-digital converters that are used to convert the samples to and from analog form. In an IEEE 802.11-compatible embodiment, the 802.11a compatible 20 MHz OFDM samples are converted to and from analog form directly, whereas a sample rate converter converts the 802.11b compatible 22 MHz DSSS samples to and from 40 MHz samples to provide compatibility with the 40 MHz analog conversions.