Invention Grant
- Patent Title: Shallow trench isolation process
- Patent Title (中): 浅沟槽隔离工艺
-
Application No.: US10341863Application Date: 2003-01-14
-
Publication No.: US07648886B2Publication Date: 2010-01-19
- Inventor: Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
- Applicant: Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
- Applicant Address: KY Grand Cayman
- Assignee: Globalfoundries Inc.
- Current Assignee: Globalfoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762
Abstract:
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.
Public/Granted literature
- US20040137742A1 Shallow trench isolation for strained silicon processes Public/Granted day:2004-07-15
Information query
IPC分类:
