发明授权
- 专利标题： Delay fault detection using latch with error sampling
- 专利标题（中）： 使用具有错误采样的锁存器延迟故障检测
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申请号： US11758124申请日： 2007-06-05
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公开(公告)号： US07653850B2公开(公告)日： 2010-01-26
- 发明人: James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
- 申请人： James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Buckley, Maschoff & Talwalkar LLC
- 主分类号： G01R31/28
- IPC分类号： G01R31/28 ; G06K5/04
摘要：
Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
公开/授权文献
- US20080307277A1 DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING 公开/授权日：2008-12-11