发明授权
US07657859B2 Method for IC wiring yield optimization, including wire widening during and after routing
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IC布线产量优化方法,包括布线期间和之后的线宽
- 专利标题: Method for IC wiring yield optimization, including wire widening during and after routing
- 专利标题(中): IC布线产量优化方法,包括布线期间和之后的线宽
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申请号: US11275076申请日: 2005-12-08
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公开(公告)号: US07657859B2公开(公告)日: 2010-02-02
- 发明人: John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
- 申请人: John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Gibb I.P. Law Firm, LLC
- 代理商 Richard M. Kotulak, Esq.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
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