发明授权
US07661055B2 Partial-parallel implementation of LDPC (Low Density Parity Check) decoders
失效
LDPC(低密度奇偶校验)解码器的部分并行实现
- 专利标题: Partial-parallel implementation of LDPC (Low Density Parity Check) decoders
- 专利标题(中): LDPC(低密度奇偶校验)解码器的部分并行实现
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申请号: US11323901申请日: 2005-12-30
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公开(公告)号: US07661055B2公开(公告)日: 2010-02-09
- 发明人: Tak K. Lee , Hau Thien Tran , Ba-Zhong Shen , Kelly Brian Cameron
- 申请人: Tak K. Lee , Hau Thien Tran , Ba-Zhong Shen , Kelly Brian Cameron
- 申请人地址: US CA Irvine
- 专利权人: Broadcom Corporation
- 当前专利权人: Broadcom Corporation
- 当前专利权人地址: US CA Irvine
- 代理机构: Garlick Harrison & Markison
- 代理商 Shayne X. Short
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.