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US07663245B2 Interposer and stacked chip package 失效
内插器和堆叠芯片封装

Interposer and stacked chip package
摘要:
An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.
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