Invention Grant
- Patent Title: Wafer level package and manufacturing method thereof
- Patent Title (中): 晶圆级封装及其制造方法
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Application No.: US12230793Application Date: 2008-09-04
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Publication No.: US07663250B2Publication Date: 2010-02-16
- Inventor: Hyung Jin Jeon , Sung Yi , Jong Yun Lee , Young Do Kweon , Jong Hwan Baek
- Applicant: Hyung Jin Jeon , Sung Yi , Jong Yun Lee , Young Do Kweon , Jong Hwan Baek
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2008-0056817 20080617
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.
Public/Granted literature
- US20090309216A1 WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2009-12-17
Information query
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