A tree-structure memory device. A tree-structure memory device comprises a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction. A plurality of layers having a plurality of memory cells is arranged in a first array. At least one tree structure corresponds to a plurality of layers and a bit line, and has a trunk portion and at least one branch portion that corresponds to one of the layers. A word-line group includes at least one word line crossing with the branch portion of the tree structure at a first intersection region. A memory cell of the first array is located at the first intersection region in a layer of the layers. The first array of memory cells includes at least one memory cell comprising a phase-change-material layer disposed between the word line and the branch portion of the tree structure at the first intersection region without an intervening current-steering element.