Invention Grant
- Patent Title: Semiconductor memory with a delay circuit
- Patent Title (中): 具有延迟电路的半导体存储器
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Application No.: US11907442Application Date: 2007-10-12
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Publication No.: US07663945B2Publication Date: 2010-02-16
- Inventor: Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
- Applicant: Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
- Applicant Address: JP Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2002-072953 20020315
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C8/18

Abstract:
A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
Public/Granted literature
- US20080056031A1 Semiconductor memory Public/Granted day:2008-03-06
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