Invention Grant
- Patent Title: Apparatus, method, and system of NAND defect management
- Patent Title (中): NAND缺陷管理的设备,方法和系统
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Application No.: US11710794Application Date: 2007-02-26
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Publication No.: US07669092B2Publication Date: 2010-02-23
- Inventor: Michael Murray
- Applicant: Michael Murray
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C16/04

Abstract:
Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group.
Public/Granted literature
- US20080209107A1 Apparatus, method, and system of NAND defect management Public/Granted day:2008-08-28
Information query