发明授权
- 专利标题: Methodology to improve turnaround for integrated circuit design using geometrical hierarchy
- 专利标题(中): 使用几何层次结构改善集成电路设计周转的方法
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申请号: US11747485申请日: 2007-05-11
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公开(公告)号: US07669175B2公开(公告)日: 2010-02-23
- 发明人: James A. Culp , Maharaj Mukherjee , Timothy G. Dunham , Mark Lavin
- 申请人: James A. Culp , Maharaj Mukherjee , Timothy G. Dunham , Mark Lavin
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Wenjie Li; Todd M. C. Li
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
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