发明授权
US07669175B2 Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效
使用几何层次结构改善集成电路设计周转的方法

Methodology to improve turnaround for integrated circuit design using geometrical hierarchy
摘要:
A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
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