发明授权
- 专利标题: Hetero junction bipolar transistor and method of manufacturing the same
- 专利标题(中): 异质结双极晶体管及其制造方法
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申请号: US11634614申请日: 2006-12-06
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公开(公告)号: US07679105B2公开(公告)日: 2010-03-16
- 发明人: Yong Won Kim , Eun Soo Nam , Ho Young Kim , Sang Seok Lee , Dong Suk Jun , Hong Yeol Lee , Seon Eui Hong , Dong Young Kim , Jong Won Lim , Myoung Sook Oh
- 申请人: Yong Won Kim , Eun Soo Nam , Ho Young Kim , Sang Seok Lee , Dong Suk Jun , Hong Yeol Lee , Seon Eui Hong , Dong Young Kim , Jong Won Lim , Myoung Sook Oh
- 申请人地址: KR Daejeon
- 专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人地址: KR Daejeon
- 代理机构: Ladas & Parry LLP
- 优先权: KR10-2005-0120171 20051208
- 主分类号: H01L29/24
- IPC分类号: H01L29/24
摘要:
Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor. The HBT includes a semi-insulating compound substrate, a sub-collector layer formed on the semi-insulating compound substrate, a pair of collector electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the sub-collector layer, a collector layer and a base layer disposed between the collector electrodes, a pair of base electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the base layer, an emitter layer stack disposed between the base electrodes, and an emitter electrode that is formed on the emitter layer stack, and includes a portion having a line width wider than the line width of the emitter layer stack, wherein both sidewalls of the emitter electrode are respectively aligned with inner walls of the pair of base electrodes, and sidewalls of the collector layer and the base layer are located between outer sidewalls of the pair of base electrodes of the pair of base electrodes.