Invention Grant
- Patent Title: Semiconductor memory device and test method thereof
- Patent Title (中): 半导体存储器件及其测试方法
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Application No.: US11773119Application Date: 2007-07-03
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Publication No.: US07679977B2Publication Date: 2010-03-16
- Inventor: Masanobu Shirakawa
- Applicant: Masanobu Shirakawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-185680 20060705
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, wherein the device has such a test mode that includes a page searching sequence for searching a fast page with the fastest write speed in the memory cell array.
Public/Granted literature
- US20080123409A1 SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF Public/Granted day:2008-05-29
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