Invention Grant
- Patent Title: Chip package structure
- Patent Title (中): 芯片封装结构
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Application No.: US11734250Application Date: 2007-04-11
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Publication No.: US07683462B2Publication Date: 2010-03-23
- Inventor: Jie-Hung Chiou , Yong-Chao Qiao , Yan-Yi Wu
- Applicant: Jie-Hung Chiou , Yong-Chao Qiao , Yan-Yi Wu
- Applicant Address: BM Bermuda
- Assignee: ChipMOS Technologies (Bermuda) Ltd.
- Current Assignee: ChipMOS Technologies (Bermuda) Ltd.
- Current Assignee Address: BM Bermuda
- Agency: Jianq Chyun IP Office
- Priority: CN200710001894 20070206
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.
Public/Granted literature
- US20080185697A1 CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME Public/Granted day:2008-08-07
Information query
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