Invention Grant
- Patent Title: Methods and apparatus for a reduced inductance wirebond array
- Patent Title (中): 减小电感引线阵列的方法和装置
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Application No.: US11393582Application Date: 2006-03-29
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Publication No.: US07683480B2Publication Date: 2010-03-23
- Inventor: Mario M. Bokatius , Peter H. Aaen , Brian W. Condie
- Applicant: Mario M. Bokatius , Peter H. Aaen , Brian W. Condie
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia, Fisher & Lorenz, P.C.
- Main IPC: H01L23/24
- IPC: H01L23/24
Abstract:
A wirebond array (100) comprising a plurality of signal wires 110 and a plurality of ground wires (120) interdigitated with and substantially parallel to the set of signal wires (110). In one embodiment, each of the plurality of signal wires (110) and ground wires (120) is attached to a first semiconductor device (102) (e.g., a microwave power device). In another, each of the plurality of signal wires (110) is further attached to a package lead (104). In one embodiment, each of the plurality of ground wires (120) is further attached to a ground connection region (106) substantially coplanar with the package lead (104). Alternatively, each of the plurality of signal wires (110) is further attached to a second semiconductor device, wherein each of the plurality of ground wires (120) is further attached to the second semiconductor device.
Public/Granted literature
- US20070235855A1 Methods and apparatus for a reduced inductance wirebond array Public/Granted day:2007-10-11
Information query
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