A wiring layer includes a signal line and covers a predetermined portion on a source region and a drain region of a crystalline silicon layer. A gate insulating layer is on the crystalline silicon layer and the wiring layer. A gate electrode layer above the gate insulating layer includes a scanning line, a gate electrode corresponding to a channel region of the crystalline silicon layer, and a capacitor electrode corresponding to a predetermined portion of the wiring layer. The capacitor electrode is formed separately from the scanning line and the gate electrode and is configured to form a capacitor with the wiring layer. An interlayer insulating film is on the gate electrode layer and the gate insulating layer. A pixel electrode layer on the interlayer insulating film includes a pixel electrode connected to the wiring layer through a contact hole in the gate insulating layer and the interlayer insulating film.