发明授权
- 专利标题： Multi-protocol low latency automatic speed negotiation architecture for an embedded high speed serial interface in a programmable logic device
- 专利标题（中）： 用于可编程逻辑器件中嵌入式高速串行接口的多协议低延迟自动速度协商架构
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申请号： US11490406申请日： 2006-07-19
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公开(公告)号： US07684477B1公开(公告)日： 2010-03-23
- 发明人: Divya Vijayaraghavan , Chong H. Lee
- 申请人： Divya Vijayaraghavan , Chong H. Lee
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Jeffrey H. Ingerman
- 主分类号： H04B3/46
- IPC分类号： H04B3/46
摘要：
A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate.Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.