Invention Grant
US07692499B2 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering
有权
使用自适应滤波的数字补偿高度稳定的保持时钟生成技术
- Patent Title: Digitally compensated highly stable holdover clock generation techniques using adaptive filtering
- Patent Title (中): 使用自适应滤波的数字补偿高度稳定的保持时钟生成技术
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Application No.: US12006368Application Date: 2007-12-31
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Publication No.: US07692499B2Publication Date: 2010-04-06
- Inventor: Xin Liu , Liang Zhang , Yong Wang
- Applicant: Xin Liu , Liang Zhang , Yong Wang
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Finnegan, Henderson, et al
- Main IPC: H03L7/093
- IPC: H03L7/093 ; H03L7/087 ; H03L1/00

Abstract:
A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.
Public/Granted literature
- US20090167443A1 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering Public/Granted day:2009-07-02
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