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US07692499B2 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering 有权
使用自适应滤波的数字补偿高度稳定的保持时钟生成技术

Digitally compensated highly stable holdover clock generation techniques using adaptive filtering
Abstract:
A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.
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