To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.