发明授权
- 专利标题: Logic design modeling and interconnection
- 专利标题(中): 逻辑设计建模与互连
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申请号: US10824489申请日: 2004-04-15
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公开(公告)号: US07698118B2公开(公告)日: 2010-04-13
- 发明人: Frederic Reblewski
- 申请人: Frederic Reblewski
- 申请人地址: US OR Wilsonville
- 专利权人: Mentor Graphics Corporation
- 当前专利权人: Mentor Graphics Corporation
- 当前专利权人地址: US OR Wilsonville
- 代理机构: Banner & Witcoff, Ltd.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H03K17/693 ; H03K19/00 ; H03K19/173 ; H03K19/177
摘要:
A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
公开/授权文献
- US20050234692A1 Logic design modeling and interconnection 公开/授权日:2005-10-20
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