Invention Grant
US07700946B2 Structure for reducing prior level edge interference with critical dimension measurement
失效
用于减小关键尺寸测量的先前水平边缘干扰的结构
- Patent Title: Structure for reducing prior level edge interference with critical dimension measurement
- Patent Title (中): 用于减小关键尺寸测量的先前水平边缘干扰的结构
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Application No.: US12056558Application Date: 2008-03-27
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Publication No.: US07700946B2Publication Date: 2010-04-20
- Inventor: Alexander L. Martin , Eric P. Solecky
- Applicant: Alexander L. Martin , Eric P. Solecky
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Wenjie Li
- Main IPC: H01L21/66
- IPC: H01L21/66
Abstract:
A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.
Public/Granted literature
- US20080173869A1 METHOD AND STRUCTURE FOR REDUCING PRIOR LEVEL EDGE INTERFERENCE WITH CRITICAL DIMENSION MEASUREMENT Public/Granted day:2008-07-24
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