Invention Grant
US07703055B2 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole 有权
使用系统故障率提高半导体集成电路器件产量的方法和系统

Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole
Abstract:
A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
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