Invention Grant
- Patent Title: Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole
- Patent Title (中): 使用系统故障率提高半导体集成电路器件产量的方法和系统
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Application No.: US11698029Application Date: 2007-01-26
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Publication No.: US07703055B2Publication Date: 2010-04-20
- Inventor: Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
- Applicant: Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2006-0008700 20060127
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
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