Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101s, a protective film 102, and the silicon nitride film 103. A gate insulating film 109 is then formed on the inner walls of the gate trenches 108, and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108. The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.