发明授权
US07710172B2 DLL circuit, semiconductor memory device using the same, and data processing system
失效
DLL电路,使用相同的半导体存储器件和数据处理系统
- 专利标题: DLL circuit, semiconductor memory device using the same, and data processing system
- 专利标题(中): DLL电路,使用相同的半导体存储器件和数据处理系统
-
申请号: US12169972申请日: 2008-07-09
-
公开(公告)号: US07710172B2公开(公告)日: 2010-05-04
- 发明人: Koji Kuroki , Yasuhiro Takai , Hiroki Fujisawa
- 申请人: Koji Kuroki , Yasuhiro Takai , Hiroki Fujisawa
- 申请人地址: JP Tokyo
- 专利权人: Elpida Memory, Inc.
- 当前专利权人: Elpida Memory, Inc.
- 当前专利权人地址: JP Tokyo
- 代理机构: Sughrue Mion, PLLC
- 优先权: JP2007-181360 20070710
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.