发明授权
- 专利标题: Block decoding methods and apparatus
- 专利标题(中): 块解码方法和装置
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申请号: US11084502申请日: 2005-03-18
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公开(公告)号: US07712013B2公开(公告)日: 2010-05-04
- 发明人: Meir Griniasty , Moti Altahan
- 申请人: Meir Griniasty , Moti Altahan
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwegman, Lundberg & Woessner, P.A.
- 主分类号: H03M13/03
- IPC分类号: H03M13/03
摘要:
In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or more existing branches within a conceptual tree diagram, calculating scores for potential paths branching from the one or more existing branches, and performing a subsequent redundancy check on a next candidate bit sequence, which corresponds to a potential path that has a next lowest score, to determine if the next candidate bit sequence is compliant.
公开/授权文献
- US20060212784A1 Block decoding methods and apparatus 公开/授权日:2006-09-21
信息查询
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