发明授权
US07713806B2 Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C
有权
通过SiGe和/或Si：C的栅极应力工程制造体硅和SOI MOS器件中无位错应力通道的结构和方法
- 专利标题： Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C
- 专利标题（中）： 通过SiGe和/或Si：C的栅极应力工程制造体硅和SOI MOS器件中无位错应力通道的结构和方法
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申请号： US12352504申请日： 2009-01-12
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公开(公告)号： US07713806B2公开(公告)日： 2010-05-11
- 发明人: Huilong Zhu , Bruce B. Doris , Huajie Chen
- 申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Scully, Scott, Murphy & Presser, P.C.
- 代理商 Joseph P. Abate, Esq.
- 主分类号： H01L21/00
- IPC分类号： H01L21/00 ; H01L21/84 ; H01L21/336 ; H01L21/8234
摘要：
Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.