发明授权
- 专利标题： Method of forming isolation regions for integrated circuits
- 专利标题（中）： 形成集成电路隔离区的方法
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申请号： US12205361申请日： 2008-09-05
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公开(公告)号： US07713834B2公开(公告)日： 2010-05-11
- 发明人: Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
- 申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
- 申请人地址： KY Grand Cayman
- 专利权人： GlobalFoundries Inc.
- 当前专利权人： GlobalFoundries Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Ditthavong, Mori & Steiner, P.C.
- 主分类号： H01L21/76
- IPC分类号： H01L21/76
摘要：
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
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