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发明授权
US07719346B2 Reference voltage circuit 有权
参考电压电路

Reference voltage circuit
摘要：
Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal (10) becomes lower and thus an NMOS transistor (71) operates in non-saturation to reduce an output resistance (ro71) of the NMOS transistor (71), when a gain (Ao) of a differential amplifier circuit (60) is large, the power supply rejection ratio (PSRRLF) is also large. Therefore, even when a minimum operating voltage of the reference voltage circuit is low, the power supply rejection ratio (PSRRLF) can be made larger. In other words, since the gain (Ao) of the differential amplifier circuit (60) contributes to the power supply rejection ratio (PSRRLF), when the gain (Ao) of the differential amplifier circuit (60) increases, the power supply rejection ratio (PSRRLF) also becomes larger by the increase.
摘要（中）：

提供了即使在电源电压低的情况下电源抑制比大的基准电压电路。 即使在电源端子（10）的电源电压变低的情况下，NMOS晶体管（71）工作在非饱和状态，以降低NMOS晶体管（71）的输出电阻（ro71），当 差分放大电路（60）的增益（Ao）大，电源抑制比（PSRRLF）也大。 因此，即使基准电压电路的最小工作电压低，也可以使电源抑制比（PSRRLF）更大。 换句话说，由于差分放大电路（60）的增益（Ao）有助于电源抑制比（PSRRLF），当差分放大电路（60）的增益（Ao）增加时，电源抑制比 （PSRRLF）也随着增加而变大。

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