Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal (10) becomes lower and thus an NMOS transistor (71) operates in non-saturation to reduce an output resistance (ro71) of the NMOS transistor (71), when a gain (Ao) of a differential amplifier circuit (60) is large, the power supply rejection ratio (PSRRLF) is also large. Therefore, even when a minimum operating voltage of the reference voltage circuit is low, the power supply rejection ratio (PSRRLF) can be made larger. In other words, since the gain (Ao) of the differential amplifier circuit (60) contributes to the power supply rejection ratio (PSRRLF), when the gain (Ao) of the differential amplifier circuit (60) increases, the power supply rejection ratio (PSRRLF) also becomes larger by the increase.