An address counter includes FIFO units and first to third command counters that controls the groups. In the FIFO units, latch circuits including input gates and output gates are connected in parallel. The first command counter conducts any one of the input gates in response to a first internal command; the second command counter conducts any one of the output gates in response to a second internal command; and the third command counter conducts any one of the output gates in response to a third internal command. Thereby, the same address signals can be outputted successively at a plurality of timings, and thus, a circuit scale of the address counter can be reduced.