发明授权
US07724575B2 Page-buffer and non-volatile semiconductor memory including page buffer
有权
页缓冲器和非易失性半导体存储器,包括页缓冲器
- 专利标题: Page-buffer and non-volatile semiconductor memory including page buffer
- 专利标题(中): 页缓冲器和非易失性半导体存储器,包括页缓冲器
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申请号: US12035028申请日: 2008-02-21
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公开(公告)号: US07724575B2公开(公告)日: 2010-05-25
- 发明人: Sung-Soo Lee , Young-Ho Lim , Hyun-Chul Cho , Dong-Hyuk Chae
- 申请人: Sung-Soo Lee , Young-Ho Lim , Hyun-Chul Cho , Dong-Hyuk Chae
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Volentine & Whitt, PLLC
- 优先权: KR2004-86450 20041028; KR2004-86451 20041028
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.
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