发明授权
US07724756B2 Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors 有权
输入/输出缓冲控制器,用于优化内存利用率并防止数据包欠载错误

  • 专利标题: Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors
  • 专利标题(中): 输入/输出缓冲控制器,用于优化内存利用率并防止数据包欠载错误
  • 申请号: US12000151
    申请日: 2007-12-10
  • 公开(公告)号: US07724756B2
    公开(公告)日: 2010-05-25
  • 发明人: Joey Chow
  • 申请人: Joey Chow
  • 申请人地址: FR Paris
  • 专利权人: Alcatel-Lucent
  • 当前专利权人: Alcatel-Lucent
  • 当前专利权人地址: FR Paris
  • 代理机构: Kramer & Amado P.C.
  • 主分类号: H04L12/54
  • IPC分类号: H04L12/54 H04L12/56
Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors
摘要:
To avoid under-run conditions that result in corrupt packets at I/O interfaces, a FIFO buffer controller monitors key aspects of the contents of FIFO buffers of I/O interfaces. The FIFO buffer controller initiates transmission of data from the FIFO buffer when at least one complete packet is stored in the FIFO buffer or when the size of a partial packet stored therein is large enough so that the remainder of the packet would normally be received by the FIFO buffer before the stored part can be transmitted from the FIFO buffer; thereby avoiding an under-run error condition.
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