发明授权
US07725619B2 Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes
失效
允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法
- 专利标题: Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes
- 专利标题(中): 允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法
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申请号: US11226967申请日: 2005-09-15
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公开(公告)号: US07725619B2公开(公告)日: 2010-05-25
- 发明人: George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
- 申请人: George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Dillon & Yudell LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00 ; G06F13/28
摘要:
A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.