A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.