发明授权
US07730284B2 Pipelined instruction processor with data bypassing and disabling circuit
有权
带数据旁路和禁用电路的流水线指令处理器
- 专利标题： Pipelined instruction processor with data bypassing and disabling circuit
- 专利标题（中）： 带数据旁路和禁用电路的流水线指令处理器
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申请号： US10549368申请日： 2004-03-17
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公开(公告)号： US07730284B2公开(公告)日： 2010-06-01
- 发明人: Balakrishnan Srinivasan , Ramanathan Sethuraman , Carlos Antonio Alba Pinto
- 申请人： Balakrishnan Srinivasan , Ramanathan Sethuraman , Carlos Antonio Alba Pinto
- 申请人地址： NL Eindhoven
- 专利权人： Koninklijke Philips Electronics N.V.
- 当前专利权人： Koninklijke Philips Electronics N.V.
- 当前专利权人地址： NL Eindhoven
- 优先权： EP031007107 20030319
- 国际申请： PCT/IB2004/050270 WO 20040317
- 国际公布： WO2004/084065 WO 20040930
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.
公开/授权文献
- US20060212686A1 Pipelined instruction processor with data bypassing 公开/授权日：2006-09-21