发明授权
US07730376B2 Providing high availability in a PCI-Express™ link in the presence of lane faults 有权
在存在通道故障的情况下,在PCI-Express™链路中提供高可用性

  • 专利标题: Providing high availability in a PCI-Express™ link in the presence of lane faults
  • 专利标题(中): 在存在通道故障的情况下,在PCI-Express™链路中提供高可用性
  • 申请号: US12056777
    申请日: 2008-03-27
  • 公开(公告)号: US07730376B2
    公开(公告)日: 2010-06-01
  • 发明人: Debendra Das Sharma
  • 申请人: Debendra Das Sharma
  • 申请人地址: US CA Santa Clara
  • 专利权人: Intel Corporation
  • 当前专利权人: Intel Corporation
  • 当前专利权人地址: US CA Santa Clara
  • 代理商 Derek J. Reynolds
  • 主分类号: G01R31/28
  • IPC分类号: G01R31/28 G06F11/00
Providing high availability in a PCI-Express™ link in the presence of lane faults
摘要:
A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.
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