发明授权
US07732313B2 FUSI integration method using SOG as a sacrificial planarization layer
有权
使用SOG作为牺牲平坦化层的FUSI积分方法
- 专利标题： FUSI integration method using SOG as a sacrificial planarization layer
- 专利标题（中）： 使用SOG作为牺牲平坦化层的FUSI积分方法
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申请号： US12348660申请日： 2009-01-05
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公开(公告)号： US07732313B2公开(公告)日： 2010-06-08
- 发明人: Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
- 申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Rose Alyssa Keagy; W. James Brady; Frederick J. Telecky, Jr.
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.