发明授权
- 专利标题: Noise-reducing transistor arrangement
- 专利标题(中): 降噪晶体管布置
-
申请号: US10583538申请日: 2004-12-03
-
公开(公告)号: US07733157B2公开(公告)日: 2010-06-08
- 发明人: Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
- 申请人: Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
- 申请人地址: DE Neubiberg
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Neubiberg
- 代理机构: Dickstein, Shapiro, LLP.
- 优先权: DE10358713 20031215
- 国际申请: PCT/DE2004/002657 WO 20041203
- 国际公布: WO2005/060099 WO 20050630
- 主分类号: H03K17/687
- IPC分类号: H03K17/687
摘要:
Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
公开/授权文献
信息查询
IPC分类: