发明授权
- 专利标题: Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon
- 专利标题(中): 形成具有不同宽度的铜布线层的半导体器件的方法,其上形成有不同厚度的金属覆盖层
-
申请号: US12325670申请日: 2008-12-01
-
公开(公告)号: US07741214B2公开(公告)日: 2010-06-22
- 发明人: Toshiyuki Takewaki , Kazuyoshi Ueno
- 申请人: Toshiyuki Takewaki , Kazuyoshi Ueno
- 申请人地址: JP Kanagawa
- 专利权人: NEC Electronics Corporation
- 当前专利权人: NEC Electronics Corporation
- 当前专利权人地址: JP Kanagawa
- 代理机构: Young & Thompson
- 优先权: JP2005-007505 20050114
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763 ; H01L21/44
摘要:
In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.
公开/授权文献
信息查询
IPC分类: