发明授权
US07750674B2 Low-power transceiver architectures for programmable logic integrated circuit devices
有权
用于可编程逻辑集成电路器件的低功耗收发器架构
- 专利标题： Low-power transceiver architectures for programmable logic integrated circuit devices
- 专利标题（中）： 用于可编程逻辑集成电路器件的低功耗收发器架构
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申请号： US12214466申请日： 2008-06-18
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公开(公告)号： US07750674B2公开(公告)日： 2010-07-06
- 发明人: Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
- 申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Robert R. Jacksor.
- 主分类号： H01L25/00
- IPC分类号： H01L25/00 ; H03K19/177
摘要：
High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.