- 专利标题: CMOS back-gated keeper technique
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申请号: US12045500申请日: 2008-03-10
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公开(公告)号: US07750682B2公开(公告)日: 2010-07-06
- 发明人: Kerry Bernstein , Andres Bryant , Wilfried Haensch
- 申请人: Kerry Bernstein , Andres Bryant , Wilfried Haensch
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P.C.
- 代理商 Vazken Alexanian
- 主分类号: H03K19/094
- IPC分类号: H03K19/094
摘要:
A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
公开/授权文献
- US20090224803A1 CMOS BACK-GATED KEEPER TECHNIQUE 公开/授权日:2009-09-10
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