Invention Grant
- Patent Title: High voltage switch with reduced voltage stress at output stage
- Patent Title (中): 输出级电压应力降低的高压开关
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Application No.: US12343773Application Date: 2008-12-24
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Publication No.: US07750689B1Publication Date: 2010-07-06
- Inventor: Vikas Rana , Abhishek Lal , Promod Kumar
- Applicant: Vikas Rana , Abhishek Lal , Promod Kumar
- Applicant Address: IN Greater Noida (UP)
- Assignee: STMicroelectronics, PVT. Ltd.
- Current Assignee: STMicroelectronics, PVT. Ltd.
- Current Assignee Address: IN Greater Noida (UP)
- Agency: Hogan Lovells US LLP
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements.
Public/Granted literature
- US20100156496A1 HIGH VOLTAGE SWITCH WITH REDUCED VOLTAGE STRESS AT OUTPUT STAGE Public/Granted day:2010-06-24
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