发明授权
- 专利标题: Phase-locked loop
- 专利标题(中): 锁相环
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申请号: US12077929申请日: 2008-03-20
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公开(公告)号: US07750696B2公开(公告)日: 2010-07-06
- 发明人: Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
- 申请人: Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
- 申请人地址: US CA San Jose
- 专利权人: Integrated Device Technology, Inc.
- 当前专利权人: Integrated Device Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Hayes and Boone LLP
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.
公开/授权文献
- US20090237132A1 Phase-locked loop 公开/授权日:2009-09-24