Invention Grant
- Patent Title: Method to minimize compatibility error in hierarchical modulation using variable phase
- Patent Title (中): 使用可变相分级调制最小化兼容性错误的方法
-
Application No.: US11474735Application Date: 2006-06-26
-
Publication No.: US07751497B2Publication Date: 2010-07-06
- Inventor: Glenn A. Walker , Eric A. Dibiaso , Michael L. Hiatt, Jr.
- Applicant: Glenn A. Walker , Eric A. Dibiaso , Michael L. Hiatt, Jr.
- Applicant Address: US MI Troy
- Assignee: Delphi Technologies, Inc.
- Current Assignee: Delphi Technologies, Inc.
- Current Assignee Address: US MI Troy
- Agent Jimmy L. Funke
- Main IPC: H04L27/20
- IPC: H04L27/20 ; H04L27/10 ; H04L27/00 ; H04L9/00 ; H04K1/10 ; H04J11/00

Abstract:
The present invention provides a method, receiver and transmitter for use in a SDAR system. The method involves generating a first modulated signal based on first input data. Additional modulation is superimposed on the first modulated signal based on additional input data, being spread across a plurality of symbols in the first modulated signal in a predetermined pattern to generate a modified signal which is then transmitted. The modified signal is decoded by performing a first demodulation of the first modulated signal then additional demodulation is performed to obtain additional input data. The superimposing step uses a plurality of offset sequence values to add the additional modulation to the first modulated signal. The offset sequence may appear as a pseudo-random distribution of offset sequence values, and may include at least one zero offset value. Alternatively, the additional modulated signal may be a formed as a direct sequence spread spectrum modulation and the offset sequence appearing as a pseudo-noise distribution. A Hadamard matrix sequence may be used as the direct sequence code.
Public/Granted literature
- US20070054614A1 Method to minimize compatibility error in hierarchical modulation using variable phase Public/Granted day:2007-03-08
Information query