Invention Grant
US07752581B2 Design structure and system for identification of defects on circuits or other arrayed products 有权
用于识别电路或其他阵列产品上的缺陷的设计结构和系统

Design structure and system for identification of defects on circuits or other arrayed products
Abstract:
A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.
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