A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about the failure analysis. The analysis screen display controller 14 generates a superimposed image in which the pattern image P1 and the layout image P3 are superimposed, as an image of the semiconductor device to be displayed by the display device 40, and sets a transmittance of the layout image P3 relative to the pattern image P1 in the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.