发明授权
- 专利标题: Method and apparatus for stacking electrical components using via to provide interconnection
- 专利标题(中): 使用通孔堆叠电气元件以提供互连的方法和装置
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申请号: US12250979申请日: 2008-10-14
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公开(公告)号: US07755188B2公开(公告)日: 2010-07-13
- 发明人: Chen Jung Tsai , Chin Wen Lin
- 申请人: Chen Jung Tsai , Chin Wen Lin
- 申请人地址: TW Hsinchu
- 专利权人: Macronix International Co., Ltd.
- 当前专利权人: Macronix International Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Stout, Uxa, Buyan & Mullins, LLP
- 主分类号: H01L23/34
- IPC分类号: H01L23/34
摘要:
An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.
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